Synopsys Test & SLM Forum
Join the design and test community at the Synopsys Test & SLM Forum to hear how industry leaders are tackling the growing complexity of semiconductor design, test, and lifecycle management. Discover how AI-driven test, advanced design-for-test, in-chip monitoring, diagnosis, and silicon analytics are being used to improve productivity, accelerate yield learning, and strengthen silicon quality and reliability. Connect with peers and Synopsys experts over cocktails, dinner, and networking.
Please register to reserve your seat.
Note: This is a customer event. All registration requests will be reviewed upon submission, and you will be notified via email if approved. Thank you for your understanding.
Event Location: Grand Hyatt San Antonio River Walk, Presidio ABC (3rd Floor)
6:00 - 6:45 pm
Cocktail Reception
6:45 - 7:00 pm
Opening Remarks & Dinner
Srikanth Raman, Product Management, Director, Synopsys
Yervant Zorian, Synopsys Fellow, Synopsys
7:00 - 7:15 pm
Accelerating DFT Closure for Multi-Die System-in-Package AI Accelerators Using TMM Flows
Wilson Pradeep, Director, DFT and Test, Tenstorrent
7:15 - 7:30 pm
A Scalable Multi-Level Test Solution for Gen-AI Compute SoCs
Pradip Thaker, PhD, India Country Head and VP, Engineering, d-Matrix
Adeeb Husnain, Principal DFT Engineer, d-Matrix
7:30 - 7:45 pm
An End-to-End HSAT Ecosystem for Large-Scale Structural Test Deployment in Advanced Networking ASICs
Vinay Kumar Kotha, Senior Technical Leader, Cisco
7:45 - 8:00 pm
In-field Memory Test and Debug with Synopsys STAR Memory System
Amit Pandey, Principal Engineer, Amazon Web Services (AWS)
8:00 - 8:20 pm
Moderated Q&A
8:20 - 9:30 pm
Networking Reception & Dessert